1. Field of the Invention
The present invention relates to a voltage level translator, which especially enhanced the speed of level translating by constituting the circuit not to make the transistor saturated in translating the TTL(Transistor-Transistor Logic) level ECL (Emitter-Coupled Logic) level.
2. Description of the Prior Art
In the Integrated Circuit of high-speed performance over LSI( Large Scale Integrated Circuit),the ECL circuit, of which the speed is high, is frequently used.
But the general outer circuit of the system is composed of TTL in many cases.
Like this, When the outer logic of the system is composed of TTL and the inner logic of the Integrated Circuit is composed of ECL, a translator which translates the TTL level to the ECL level (hereinafter referred to as TTL to ECL level translator) is indispensible and has been introduced many times up to now, but the time in translating the level has always been the problem.
Generally, the traditional TTL to ECL level translator uses the TTL input circuit as shown in FIG. 2 or DTL(Diode-Transistor-Logic) input circuit as shown in FIG. 3.
But the DTL input circuit is generally slower than TTL, and in the TTL input circuit as shown in FIG. 2, there has been the problem that the speed of data processing is lowered because of the phenomenon of the transistor Q.sub.1 being saturated.